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T100/8 Fast Data Acquisition Board
The T100/8 is a very fast data acquisition
board with huge internal memory. The board consists of a carrier PCB which
can be supplied with either one or two analog modules. A T100/8-1 can
be upgraded later on with a second analog module to a T100/8-2. The carrier
PCB holds the digital circuitry for the experiment control and interface
to the ISA- or PCI-bus, the board's memory and the DC/DC converters for
the regulated power supply of the analog modules.
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Furthermore, boards of the type T3012, T112, T114 and T100/8 can be combined to systems with different conversion rates and resolution bits. These systems are called heterogeneous multi-board-systems. As not all off the boards will allow exactly the same sampling speeds, the boards are sampled individually. The triggering of the different boards may, however, still be synchronised by the trigger-bus. Analog Inputs Each analog input module has its own amplifier, gain can be adjusted individually by software control. Input ranges are unipolar from 0-200mV to 0-10V and bipolar from +/- 100mV to +/- 5V. A software adjustable offset can smoothly be varied from unipolar to bipolar input ranges in more than 4000 steps. Input impedance of each channel is 1MOhm/18pF. The analog bandwidth is ³45MHz for all gains. To connect high-frequency-signals to the inputs, a switchable 50 Ohms termination is supplied for each input. Each channel has an 8bit A/D converter with a maximum sampling rate of 100MHz. Both modules start converting at exactly the same time. Automatic calibration of gain and offset is achieved with a 12 bit DA-converter. Digital and analog circuitry are strictly separated, the analog power is carefully decoupled from the PC power and a multitude of shielding layers is used on both sides of the sensitive analog circuitry. This altogether gives rise to extremely good signal-to-noise-ratio. The strict channel separating is secured by separated signal inputs with gold plated miniature coaxial connectors (SMA-plugs). For comfortable using adapters to the common BNC-connectors will be delivered with the board. Each channel has its own trigger unit, allowing to set up individual trigger levels. Hereby it is possible to select either one of the both channels as a trigger source. It is also possible to select a combination of both channels and the external trigger input as trigger source. Therefore powerful many-channel-trigger-modes like a pattern-trigger or state-trigger are implemented. Ringbuffer The standard operation of fast data acquisition hardware is a ring buffer: data are acquired and stored in a cyclic memory until a trigger event is registered. Then a preloadable posttrigger counter is decremented to zero and stops the acquisition. Thus the ringbuffer can be divided in pre- and posttrigger domains. Data recorded before the start of the posttrigger counter is in the pretrigger domain, data recorded after the start of the counter is in the posttrigger domain. The size of the pre- and posttrigger domain can be set by the user. After the experiment has finished, all data are transferred to the PC. For sampling rates above the maximum transfer rates of the bus (on the order of 2 .. 2.5 MBytes/s for the ISA bus and on the order of 30MB/s for the PCI bus) this ringbuffer operation is the only possible way of acquiring data. This mode of operation allows maximum sampling rates. The largest data-set recordable in this mode is given by the amount of on-board memory. On-board memory Memory size for an experiment can be adjusted from 256 samples per channel to the maximum size in steps of two. In standard configuration, the T100/8 is delivered with memory for 512kSamples (256kSamples / channel). Optional memory sizes are 2M, 4M and 8MSamples. Each analog module owns half of this memory. If the board is delivered with only one analog module, only half the memory is present. Upgrading the board with larger memory or with a second analog module can be done at any time. Memory Segmentation If traces with close-lying trigger events are to be recorded, the need to transfer the acquired data to the PC can be fatal, because the board will miss any trigger event occurring during the time of data transfer. To get around this limitation, the memory of the T100/8 can be split up into segments (blocks). Data acquisition can continue with virtually no dead-time between the end of trace n and the trigger of trace n+1, as long as there is memory left to take up the new traces. Only after all segments are filled, the data are transferred to the PC. Possible block sizes are 256, 512, 1k, 2k, 4k, 8k, 16k, 32k, 64k and 128 kSamples for each channel. This feature is optional. Timebase Both analog modules are clocked with a common timebase. This leads to absolute synchronicity of the sampled data of all 8 channels. The clock is generated in a PLL circuit, providing a fine tunability of the sampling frequencies but still conserving the high stability of the driving quartz. This may be of special interest for frequency-domain (FFT) investigations. An SMB (ISA)/SMR (PCI) connector allows to supply an external clock as sampling clock. When operating multiple boards synchronicity is provided by generating the clock signal only on the masterboard and distributing it via the coaxial multi-board-bus to the slave-boards. Triggering The trigger logic makes use of the digitised data only. This on one hand gives rise to easy reconfiguration and high stability, on the other hand it gives the possibility to use many different trigger modes. These modes may contain sophisticated combinations of trigger levels, arm levels of one or more channels and time conditions. Each channel has two comparator levels, adjustable in 256 steps. The standard trigger-modes are edge, window, pulse, period, slew and autorun. Each of this modes has a bunch of sub-parameters allowing to implement a great variety of trigger conditions. Triggersources can be either one of the both channels, the external trigger-input or any logical combination of these three. The external trigger-input allows synchronisation of the data acquisition with an external event, given by a TTL compatible signal. Under multi-board-operation another possible triggersource is the trigger-bus. The trigger-bus can be configured either in a way that all boards are triggered by a master-board, or in a way that all boards are triggered, if any board registers a trigger event. The memory can be divided in pre- and posttrigger domains, depending on how much data you like to record before and after the trigger event. Software and Installation The board is always delivered with a bundle of drivers and test routines. The drivers support programmers working under Windows (all languages that support DLL calls). A special library is provided for National Instruments' LabVIEW. All these drivers allow access to any of the boards features, all settings and all available information. They allow programmers to build there own application doing experiments of any complexity and interfacing any data acquisition or analysis applications. The test routines are delivered as executables and source code and may serve to verify correct operation of the board as well as being a starting point for own programs. Installing the software is simple, as neither DMA channels nor interrupt channels are needed. The optionally available programs SCOPE (DOS) and INSIGHT(Windows) allow to make optimum use of the boards abilities. The graphical display of SCOPE and INSIGHT is designed for optimum speed, so working with the software is very much like working with an analog scope. In addition to the well-known DSO functions like zooming and cursors both programs also offer features like auto-save (automatically stores each data set to hard-disk), support of multiple windows, printers and plotters and data conversion for many common data analysis packages. Furthermore X/Y display and Fourier-transform are possible. |
Technical Data T100/8-2 / T100/8-1
| no of channels | max. 2 analog inputs | |||
| analog bandwidth | all gains | 0 .. ³ 45 MHz (3dB) | ||
| sensitivity | 0,78 mV/digit ... 39 mV/digit | |||
| input ranges (full-scale) | bipolar: | ±100mV, ±200mV, ±250mV, ±500mV, ±1V, ±2V, ±2,5V, ±5V | ||
| unipolar: | 0..200mV, 0..400mV, 0..500mV, 0..1V, 0..2V, 0..4V, 0..5V, 0..10V | |||
| input impedance | 1 MOhm/18 pF or 50 Ohms (software switchable) | |||
| coupling | DC, 50 Ohms or GND | |||
| overvoltage at the inputs | 20 V | |||
| resolution | 8 bit | |||
| max., linearity error | 0,7 % | |||
| timebases | all channels share a common timebase | |||
| sampling rate | single-board-operation | 100 MHz...DC
(granularity < 1%) or external Clk (DC .. 50 MHz) |
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| multi-board-operation | Masterclock, internal clock, external clock | |||
| external
clock input SMB (ISA) / SMR (PCI) |
TTL-level | |||
| trigger | digital
trigger-logic Standard-Triggermodes: Edge, Window, Pulse, Slew, Period, Autorun |
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| trigger levels | 2 trigger levels per analog input, digitally adjustable in 256 steps | |||
| trigger source | channel 1, channel 2, external, pattern, triggerbus | |||
| pre-trigger | -99% .. +99% | |||
| external
trigger input SMB (ISA) / SMR (PCI) |
TTL-level | |||
| operation modes | SINGLE, RUN, autosave, multiboard | |||
| memory size T100/8-2 (standard) | each channel | 256 Samples - 256 kSamples | ||
| gain and offset calibration | automatically with internal 12bit DA converter | |||
| power consumption | + 5V/1,6A; + 12V/800mA (T100/8-1: + 5V/1,6A + 12V/400mA) | |||
| dimensions (without bracket) ISA-board | 340mm
x 105mm x 20mm (length, height, width) IBM AT compatible |
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| dimensions (without bracket) PCI-board | 313mm
x 105mm x 20mm (length, height, width) confirms to PCI-specification 2.1 |
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| OPTIONS: | ||||
| memory expansion T100/8-2 (standard 512 kSamples) | to 2 MSamples, 4 MSamples, 8 MSamples | |||
| memory expansion T100/8-1 (standard 256 kSamples) | to 1 MSamples, 2 MSamples, 4 MSamples | |||
| memory segmentation | acquisition
of events with close-lying triggers. Block sizes: 256, 512, 1k, 2k, 4k, 8k, 16k, 32k , 64k and 128 kSamples |
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